A synchronous dynamic random access memory (SDRAM) device performs at higher clock speeds than other types of memory devices by generating data which is synchronous with the clock of a central processing unit (CPU) communicating with the SDRAM. One type of SDRAM device is the Double Data Rate SDRAM (DDR-1), which, because it is able to read and/or write data on both the rising and falling edges of a clock signal supplied to the DDR-1, supports higher bandwidths than other types of memory devices.
In systems comprising a DDR-1 memory device, data is typically transferred between an application-specific integrated circuit (ASIC) and the DDR-1 via a multiple-bit data bus. Read/write operations from and to the DDR-1 are controlled using a system clock (CLK). However, variations in process, voltage and temperature (commonly known as PVT) may cause the CLK to become poorly synchronized with the data valid windows (i.e., time periods where all bits on the multiple-bit data bus have stabilized). This poor synchronization results in data that is improperly read from or written to the DDR-1.
Such poor synchronization is often corrected by substituting a strobe signal in place of the CLK when reading or writing data. As known to those of ordinary skill in the art, strobe signals flow in the same direction as the data, thus subjecting the strobe signals to the same PVT variations as the data bits. In the case of a read operation, for example, the strobe signal is generated by the DDR-1 and the data is pulled from the DDR-1, as well. In this case, both the data and the strobe signal flow from the DDR-1 to the ASIC. Thus, any PVT effects encountered by the data bits (e.g., length of metal traces from the DDR-1 to the ASIC reading the data) also are encountered by the strobe signal. For this reason, the data valid windows stay well-synchronized with the strobe signal. In turn, a delay locked loop (DLL) on the DDR-1 is used to keep the strobe signals well-synchronized with the system CLK, so that when the data bits finally reach the ASIC, the data bits may be synchronized to the system CLK so that the ASIC may use the data bits as necessary. Because these timing parameters are kept well-synchronized with each other (i.e., the data bits, the strobe signals and the system CLK), the system clock cycles at which the data bits may be synchronized to the system clock are predictable.
Because power efficiency is a substantial concern in wireless/mobile applications (e.g., mobile phones), DLLs are often omitted in DDR devices used in mobile applications (M-DDR). Although the omission of DLLs results in considerable power savings, the aforementioned strobe signals are no longer kept well-synchronized with the system CLK. Thus, once data bits arrive at the ASIC, it is difficult to synchronize them to the system CLK. If the bits cannot be synchronized to the system CLK, they cannot be used by the ASIC and are virtually useless. Furthermore, because variations in PVT may cause the synchronization between strobe signals and the system CLK to be offset by anywhere between +2 ns and +7 ns or more, the timing parameters (i.e., the relationship between data bits, strobe signals and system CLK) are considered to be unacceptably unpredictable. For this reason, M-DDR devices and DDR-1 devices on the same system cannot successfully share a single data path and instead use multiple data paths, thereby increasing manufacturing costs.